Revolutionary Advance in Flash Memory

amirm

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Flash memory is the unsung hero of our mobile computing. Can you imagine lugging around a hard disk in your phone to store your content? Toshiba Invented NAND Flash some 25 years ago. It took it quite some time for it to become dense enough to take the place of hard disks in many applications. But that era is upon us. Flash memory uses some of the smallest cells in semiconductor process to achieve its very high density. Semiconductor process though, often hits limits where making things smaller can make them very unreliable. The story below shows an innovative solution from Samsung (#1 Flash memory vendor in the world with Toshiba holding #2), to build the cells in a 3-d structure as opposed to flat as integrated circuits are built. This provides much more headroom to keep increasing the capacity of the flash memory without reducing its reliability.

This is wonderful news for all of us.

http://www.tomshardware.com/news/V-NAND-Charge-Trap-Flash-NAND-3D-silicon-nitride,23803.html

Samsung Mass Producing 3D Vertical NAND Flash

A new era in flash NAND has begun.

Samsung Electronics said on Monday that it is now mass producing the industry's first 3D Vertical NAND (V-NAND) flash memory, offering a 128 gigabit (Gb) density in a single chip.

According to Samsung, V-NAND breaks away from the floating gate-based planar structure that has been used in conventional memory over the past 40 years. It does this by utilizing the company’s proprietary vertical cell structure based on 3D Charge Trap Flash (CTF) technology, and vertical interconnect process technology to link the 3D cell array. By applying both of these technologies, it's able to provide over twice the scaling of 20nm-class planar NAND flash.

With manufacturing process shrinking down to 10 nm levels and beyond, there has been growing concern about a limit to scalability due to cell-to-cell interference that causes a trade-off in the reliability of NAND flash products. The new V-NAND solves this problem by vertically stacking planar cells, a method that was finally achieved after revamping Samsung's CTF architecture which went into development back in 2006.

"In Samsung’s CTF-based NAND flash architecture, an electric charge is temporarily placed in a holding chamber of the non-conductive layer of flash that is composed of silicon nitride (SiN), instead of using a floating gate to prevent interference between neighboring cells," the company explained. "By making this CTF layer three-dimensional, the reliability and speed of the NAND memory have improved sharply."

Samsung said its vertical interconnect process technology can stack as many as 24 cell layers vertically, using a special etching technology that connects the layers electronically by punching holes from the highest layer to the bottom. Thus by using a vertical structure, higher density NAND products can be achieved by increasing the 3D cell layers without having to continue planar scaling.

Samsung said the 3D V-NAND shows an increase of a minimum of 2X to a maximum 10X higher reliability, and twice the write performance over conventional 10nm-class floating gate NAND flash memory.

"The new 3D V-NAND flash technology is the result of our employees’ years of efforts to push beyond conventional ways of thinking and pursue much more innovative approaches in overcoming limitations in the design of memory semiconductor technology," said Jeong-Hyuk Choi, senior vice president, flash product & technology, Samsung Electronics. "Following the world’s first mass production of 3D Vertical NAND, we will continue to introduce 3D V-NAND products with improved performance and higher density, which will contribute to further growth of the global memory industry."

Nearly ten years of research was dumped into 3D Vertical NAND, the company said, and it now has more than 300 patent-pending 3D memory technologies worldwide. The new 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid state drives (SSDs).
 

JackD201

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English Amir, English! :D
 

Phelonious Ponk

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English Amir, English! :D

Massive storage in mobile devices and thumb drives, that don't lose their content. Fast, dead silent storage in laptops. Expensive at first, falling rapidly. Rapidly enough? The end of the hard drive at the sub server level.

Tim
 

garylkoh

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English Amir, English! :D

We started with 1-dimensional (1D) storage - like tape in a reel/LPs/CDs/hard-discs, etc. Then went to 2D - which is like a chessboard, where any square is addressable by a combination of X and Y coordinated. This latest is 3D - which is like a warehouse, where you can address by X,Y,Z coordinates.
 

Phelonious Ponk

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We started with 1-dimensional (1D) storage - like tape in a reel/LPs/CDs/hard-discs, etc. Then went to 2D - which is like a chessboard, where any square is addressable by a combination of X and Y coordinated. This latest is 3D - which is like a warehouse, where you can address by X,Y,Z coordinates.

Mo, betta, fasta...:)

Tim
 

JackD201

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Thanks Tim :D That was easy enough.

Gary, still some French in there but I got it. ;)
 

DonH50

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Jun 22, 2010
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Hope they're getting the power down... Not a big issue with the small memories in portable devices, but in SSDs a significant problem. 3D should help by reducing the drive (current requirements) of IO drivers and hopefully internal R/W buffers.
 

amirm

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English Amir, English! :D
Sorry, I have been under the weather lately and didn't explain as much as I should :).

Hugely oversimplifying, the process of making a semiconductor chip is a bit like photography. A "picture" of the circuit with all of its individual building blocks (flash storage in this case) is projected on a flat material and then what is not needed is etched away. As Gary mentioned, by definition this process then is in two dimensions. Making chips larger to get more storage out of them will make the yields go down. The reduction is power of 3 so doubling a chip size will make it cost 8X higher! So the effort is always in the direction of making the individual elements smaller and smaller to get more goodies in the same chip size. This is the "10 micron" reference in the article which is the next "shrink" in the sizes of the basic elements.

The problem is that the elements are getting so small that they are approaching the sizes of atoms and such. Small elements can't hold much charge. You breath on them and the number of electrons goes down, resulting in reading a faulty value (0 vs 1). There are many mitigations around this which Flash memory uses such as redundancy (throwing out bad bits).

What Samsung has done here is to go in vertical direction to build the individual cells. Imagine if I could turn a cell draw on a piece of paper sideways. It would take less space in XY dimension now. And size vertical space is not a shortage, we could make the cells bigger and stronger and hence they claim about increased reliability.

Now, stuff like this happens all the time in the lab. I could make one of any contraption this way. The trick is to have it be mass producible and cheap. Otherwise, you are just better off putting multiple chips together in the same package (which is what is done today). That is what Samsung says they have accomplished. A process where the can interconnect the vertical components very cheaply and fast. This is what the reference to "punching holes" means in the article.

I hope this hugely simplified explanation helps. The actual processes are much more complex.
 

Phelonious Ponk

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English translation:

Old chip? A big mid-50s ranch. A few thousand square feet takes up a whole lot of expensive real estate.

New Chip: High-rise. The land mass of a pre-war bungalow efficiently houses a whole neighborhood full of data.

I probably simplified that beyond belief, but it was fun.

Tim
 

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